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44 résultats
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triés par
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SIRA: Schedule Independent Register Allocation for Software PipeliningWorkshop on Compilers for Parallel Computers, Jun 2001, Edinburgh, United Kingdom
Communication dans un congrès
hal-00647138v1
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BlindBuilder : a new encoding to evolve Lego-like structuresEUROGP 2006, EvoNet, Apr 2006, Budapest, Hungary, pp.61--72
Communication dans un congrès
inria-00000995v1
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Register Saturation in Superscalar and VLIW Codes10th International Conference (CC 2001), Held as Part of the Joint European Conferences on Theory and Practice of Software (ETAPS 2001), Apr 2001, Gênes, Italy. pp.213-228, ⟨10.1007/3-540-45306-7_15⟩
Communication dans un congrès
inria-00637277v1
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Register Saturation in Data Dependence Graphs[Research Report] RR-3978, INRIA. 2000
Rapport
inria-00072669v1
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On the Equivalence of Two Systems of Affine Recurrence EquationsRR-4285, INRIA. 2001
Rapport
inria-00072302v1
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Maximizing for Reducing the Register Need in Acyclic Schedules5th International Workshop on Software and Compilers for Embedded Systems, SCOPES '2001, Embedded Systems Group, CS Dept. University Dortmund and ICD e.V., Mar 2001, St Goar, Germany
Communication dans un congrès
hal-00646770v1
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Impact des latences des loads sur l'allocation de registres dans les boucles vectorielles[Interne] 2001
Rapport
hal-00648274v1
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Application Domain-Driven System Design for Pervasive Video ProcessingTwan Basten and Marc Geilen and Harmke de Groot. Ambient Intelligence: Impact on Embedded-System Design, Kluwer Academic Press, pp.251--270, 2003
Chapitre d'ouvrage
hal-01257306v1
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Early Control of Register Pressure for Software Pipelined Loops12th International Conference (CC 2003), Held as Part of the Joint European Conferences on Theory and Practice of Software (ETAPS 2003), Apr 2003, Varsovie, Poland. pp.17-32, ⟨10.1007/3-540-36579-6_2⟩
Communication dans un congrès
inria-00637264v1
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Optimisation de programmes annotés par des assertionsRR-3983, INRIA. 2000
Rapport
inria-00072664v1
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Optimal Register Saturation in Acyclic Superscalar and VLIW CodesRR-4263, INRIA. 2001
Rapport
inria-00072324v1
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Data Prefetching and Targeted Loop Optimizations[Research Report] M2.D2, 1999, pp.47
Rapport
hal-00647624v1
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The MHAOTEU Toolset16th IMACS world congress 2000 on scientific computation, applied mathematics and simulation (IMACS'2000), Ecole polytechnique fédérale de Lausanne, Aug 2000, Lausanne, Switzerland. pp.6
Communication dans un congrès
hal-00648211v1
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Register Pressure in Instruction Level ParallelismOther [cs.OH]. Université de Versailles-Saint Quentin en Yvelines, 2002. English. ⟨NNT : ⟩
Thèse
tel-00007405v1
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Instancewise Program AnalysisRR-5117, INRIA. 2004
Rapport
inria-00071465v1
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Intraprocedural Pointer Analysis for Container-Centric ApplicationsRR-4289, INRIA. 2001
Rapport
inria-00072298v1
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Optimal Loop Parallelization under Register Constraints[Research Report] RR-2781, INRIA. 1996
Rapport
inria-00073911v1
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EquiMax. A New Formulation of Acyclic Scheduling Problem for ILP ProcessorsGyungho and Pen-Chung Yew. Interaction between Compilers and Computer Architecture, Kluwer Academic Publishers, 2001, 0-7923-7370-7
Chapitre d'ouvrage
hal-00646739v1
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Interaction with Programers[Research Report] M3.D3 - Part 2, 2001, pp.62
Rapport
hal-00647737v1
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Process for Optimizing an Application[Research Report] M3.D3 - Part 1, 2000, pp.29
Rapport
hal-00647613v1
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Cyclic Register Pressure and Allocation for Modulo Scheduled Loops[Research Report] RR-4442, INRIA. 2002
Rapport
inria-00072146v1
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Putting Polyhedral Loop Transformations to Work[Research Report] RR-4902, INRIA. 2003
Rapport
inria-00071681v1
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LoRA: a Package for Loop Optimal Register Allocation[Research Report] RR-3709, INRIA. 1999
Rapport
inria-00072959v1
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Flexible Issue Slot Assignment for VLIW Architectures[Research Report] RR-3784, INRIA. 1999
Rapport
inria-00072876v1
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Static Analysis for Guarded CodeRR-3979, INRIA. 2000
Rapport
inria-00072668v1
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Étude expérimentale sur le besoin en registres dans les boucles vectorielles[Interne] 2001
Rapport
hal-00648287v1
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Étude des Performances de Codes sur les Processeurs à Parallélisme d'Instructions : Synthèse sur la Recherche et les Outils[Intern report] 1999
Rapport
hal-00648305v1
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Array Dataflow Analysis in Presence of Non-affine Constraintsdomain_stic. Université de Versailles-Saint Quentin en Yvelines, 1998. English. ⟨NNT : ⟩
Thèse
tel-00277799v1
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Circular-arc Graph Coloring and UnrollingRR-3336, INRIA. 1998
Rapport
inria-00073353v1
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Multi-Periodic Process Networks: Prototyping and Verifying Stream-Processing SystemsEuro-Par 2002, Parallel Processing, 8th International Euro-Par Conference , Aug 2002, Paderborn, Germany
Communication dans un congrès
hal-01257309v1
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