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Managing SMT Resource Usage through Speculative Instruction Window Weighting

Hans Vandierendonck , André Seznec
[Research Report] RR-7103, INRIA. 2009, pp.22
Rapport inria-00433081v2
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Storage Free Confidence Estimation for the TAGE branch predictor

André Seznec
[Research Report] RR-7371, INRIA. 2010, pp.20
Rapport inria-00512130v2

Managing SMT resource usage through speculative instruction window weighting

Hans Vandierendonck , André Seznec
ACM Transactions on Architecture and Code Optimization, 2011, ⟨10.1145/2019608.2019611⟩
Article dans une revue hal-00639171v1

The performance vulnerability of architectural and non-architectural arrays to permanent faults

Damien Hardy , Isidoros Sideris , Nikolas Ladas , Yiannakis Sazeides
MICRO 45, Dec 2012, Vancouver, Canada
Communication dans un congrès hal-00747488v1
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Performance Upper Bound Analysis and Optimization of SGEMM on Fermi and Kepler GPUs

Junjie Lai , André Seznec
CGO '13 - 2013 International Symposium on Code Generation and Optimization, Feb 2013, Shenzhen, China
Communication dans un congrès hal-00789958v1

An Improved Preemption Delay Upper Bound for Floating Non-Preemptive Region Scheduling

José Marinho , Vincent Nélis , Stefan M. Petters , Isabelle Puaut
7th IEEE International Symposium on Industrial Embedded Systems (SIES'12), Jun 2012, Karlsruhe, Germany
Communication dans un congrès hal-00737580v1

Efficient Out-of-Order Execution of Guarded ISAs

Nathanaël Prémillieu , André Seznec
ACM Transactions on Architecture and Code Optimization, 2014, pp.21. ⟨10.1145/2677037⟩
Article dans une revue hal-01103230v1
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Sequential Performance: Raising Awareness of the Gory Details

Erven Rohou , David Guyon
International Conference on Computational Science, Jun 2015, Reykjavik, Iceland. ⟨10.1016/j.procs.2015.05.347⟩
Communication dans un congrès hal-01162336v1

On-Stack Replacement to Improve JIT-based Obfuscation - A Preliminary Study

Marwa Yusuf , Ahmed El-Mahdy , Erven Rohou
International Japan-Egypt Conference on Electronics, Communications, and Computers, Dec 2013, Cairo, Egypt
Communication dans un congrès hal-00909722v1

An Analytical Framework for Estimating TCO and Exploring Data Center Design Space

Damien Hardy , Marios Kleanthous , Isidoros Sideris , Ali Saidi , Emre Ozer , et al.
IEEE International Symposium on Performance Analysis of Systems and Software, Apr 2013, Austin, United States
Communication dans un congrès hal-00914593v1
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SPAC: A Synergistic Prefetcher Aggressiveness Controller for Multi-core Systems

Biswabandan Panda
IEEE Transactions on Computers, 2016, ⟨10.1109/TC.2016.2547392⟩
Article dans une revue hal-01307538v2
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Zero-Content Augmented Caches

Julien Dusser , Thomas Piquet , André Seznec
ICS 2009 : 23rd International Conference on Supercomputing, Jun 2009, New York, United States. ⟨10.1145/1542275.1542288⟩
Communication dans un congrès inria-00374524v1
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Proposition for a sequential accelerator in future general-purpose manycore processors

Pierre Michaud , Yiannakis Sazeides , André Seznec
[Research Report] RR-7106, INRIA. 2009
Rapport inria-00433234v3
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Best-Offset Hardware Prefetching

Pierre Michaud
International Symposium on High-Performance Computer Architecture, Mar 2016, Barcelona, Spain. ⟨10.1109/HPCA.2016.7446087⟩
Communication dans un congrès hal-01254863v1
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Revisiting Symbiotic Job Scheduling

Stijn Eyerman , Pierre Michaud , Wouter Rogiest
IEEE International Symposium on Performance Analysis of Systems and Software, Mar 2015, Philadelphia, United States. ⟨10.1109/ISPASS.2015.7095791⟩
Communication dans un congrès hal-01139807v1
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Processor Virtualization and Split Compilation for Heterogeneous Multicore Embedded Systems

Albert Cohen , Erven Rohou
47th Annual Design Automation Conference, Jun 2010, Anaheim, CA, United States
Communication dans un congrès inria-00472274v1
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Classification and Elimination of Conflicts in Hardware Transactional Memory Systems

Mridha Mohammad Waliullah , Per Stenstrom
23rd International Symposium on Computer Architecture and High Performance Computing - SBAC-PAD'2011, Oct 2011, Vitoria, Brazil
Communication dans un congrès hal-00640813v1

Static probabilistic Worst Case Execution Time Estimation for architectures with Faulty Instruction Caches

Damien Hardy , Isabelle Puaut
21st International Conference on Real-Time Networks and Systems, Oct 2013, Sophia Antipolis, France. ⟨10.1145/2516821.2516842⟩
Communication dans un congrès hal-00862604v1
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Bound the Peak Performance of SGEMM on GPU with software-controlled fast memory

Junjie Lai , André Seznec
[Research Report] RR-7923, INRIA. 2012
Rapport hal-00686006v2

Break Down GPU Execution Time with an Analytical Method

Junjie Lai , André Seznec
Rapido '12, Jan 2012, Paris, France. ⟨10.1145/2162131.2162136⟩
Communication dans un congrès hal-00764874v1
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Intercepting Functions for Memoization: A Case Study Using Transcendental Functions

Arjun Suresh , Bharath Narasimha Swamy , Erven Rohou , André Seznec
ACM Transactions on Architecture and Code Optimization, 2015, 12 (2), pp.23. ⟨10.1145/2751559⟩
Article dans une revue hal-01178085v1

An Empirical High Level Performance Model For Future Many-cores

Surya Narayanan Natarajan , Bharath Narasimha Swamy , André Seznec
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015, Ischia, Italy. ⟨10.1145/2742854.2742867⟩
Communication dans un congrès hal-01170038v1
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Scheduling of parallel applications on many-core architectures with caches: bridging the gap between WCET analysis and schedulability analysis

Viet Anh Nguyen , Damien Hardy , Isabelle Puaut
9th Junior Researcher Workshop on Real-Time Computing (JRWRTC 2015), Nov 2015, Lille, France
Communication dans un congrès hal-01236191v1
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BADCO: Behavioral Application-Dependent Superscalar Core Model

Ricardo A. Velasquez , Pierre Michaud , André Seznec
SAMOS XII: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, Jul 2012, Samos, Greece
Communication dans un congrès hal-00707346v1
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Cost-Effective Speculative Scheduling in High Performance Processors

Arthur Perais , André Seznec , Pierre Michaud , Andreas Sembrant , Erik Hagersten
International Symposium on Computer Architecture, ACM/IEEE, Jun 2015, Portland, United States. pp.247-259, ⟨10.1145/2749469.2749470⟩
Communication dans un congrès hal-01193233v1
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STiMuL: a Software for Modeling Steady-State Temperature in Multilayers - Description and user manual

Pierre Michaud
[Technical Report] RT-0385, INRIA. 2010
Rapport inria-00474286v1
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Replacement policies for shared caches on symmetric multicores : a programmer-centric point of view

Pierre Michaud
6th International Conference on High-Performance and Embedded Architectures and Compilers, Jan 2011, Heraklion, Greece. ⟨10.1145/1944862.1944890⟩
Communication dans un congrès inria-00531188v1

The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices

Marco Solinas , Rosa M. Badia , François Bodin , Albert Cohen , Paraskevas Evripidou , et al.
DSD, Sep 2013, Los Alamitos, United States. pp.272-279
Communication dans un congrès hal-00920903v1
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Intercepting functions for memoization

Arjun Suresh
Programming Languages [cs.PL]. Université de Rennes, 2016. English. ⟨NNT : 2016REN1S106⟩
Thèse tel-01410539v2
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CLI-Based Compilation Flows for the C Language

Erven Rohou , Andrea C. Ornstein , Marco Cornero
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, Jul 2010, Samos, Greece. pp.162-169, ⟨10.1109/ICSAMOS.2010.5642069⟩
Communication dans un congrès inria-00505640v1