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156 résultats
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Stream and Memory Hierarchy Design for Multi-Purpose Accelerators1st Workshop on SoC Architecture, Accelerators and Workloads (SAW-1), Jan 2010, Bangalore, India
Communication dans un congrès
inria-00633580v1
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Convex Hulls on Cellular Spaces: Spatial Computing on Cellular AutomataSASOW: Self-Adaptive and Self-Organizing Systems Workshop, Oct 2011, Ann Arbor, MI, United States. pp.67-72, ⟨10.1109/SASOW.2011.14⟩
Communication dans un congrès
hal-01799315v1
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Budgeted Region Sampling (BeeRS): Do Not Separate Sampling From Warm-Up, And Then Spend Wisely Your Simulation Budget5th IEEE International Symposium on Signal Processing and Information Technology, Dec 2005, Athens, Greece
Communication dans un congrès
inria-00001061v2
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The Potential of Synergistic Static, Dynamic and Speculative Loop Nest Optimizations for Automatic ParallelizationPespma 2010 - Workshop on Parallel Execution of Sequential Programs on Multi-core Architecture, Jun 2010, Saint Malo, France
Communication dans un congrès
inria-00494305v1
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MicroLib: A Case for the Quantitative Comparison of Micro-ArchitectureMechanismsWorkshop on Duplicating, Deconstructing, and Debunking, Jun 2004, Munich, Germany
Communication dans un congrès
inria-00001109v1
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Processor Virtualization and Split Compilation for Heterogeneous Multicore Embedded Systems47th Annual Design Automation Conference, Jun 2010, Anaheim, CA, United States
Communication dans un congrès
inria-00472274v1
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Automatic Abstraction and Fault Tolerance in Cortical Microachitectures38th ACM/IEEE International Symposium on Computer Architecture, ISCA 2011, Jun 2011, San Jose, CA, United States
Communication dans un congrès
inria-00579771v1
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Using The Meeting Graph Framework to Minimise Kernel Loop Unrolling for Scheduled Loops22nd International Workshop on Languages and Compilers for Parallel Computing (LCPC 2009), Oct 2009, Newark, United States. pp.278-292, ⟨10.1007/978-3-642-13374-9_19⟩
Communication dans un congrès
hal-00643759v1
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Processor design-space exploration through fast simulationOther [cs.OH]. Université Paris Sud - Paris XI, 2011. English. ⟨NNT : 2011PA112062⟩
Thèse
tel-00691175v1
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Periodic register saturation in innermost loopsParallel Computing, 2009, 35 (4), pp.239-254. ⟨10.1016/j.parco.2008.12.001⟩
Article dans une revue
inria-00636073v1
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Robustness of the critical behaviour in a discrete stochastic reaction-diffusion mediumIWNC'09, 2009, Himeji, Japan
Communication dans un congrès
inria-00396473v1
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Memory Interface for Multi-Purpose Multi-Stream AcceleratorsInternational Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2010, 2010, Scottsdale, AZ, United States
Communication dans un congrès
inria-00633587v1
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Facilitating the Exploration of Compositions of Program Transformations[Research Report] RR-5114, INRIA. 2004
Rapport
inria-00071468v1
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Transforming GCC into a research-friendly environment: plugins for optimization tuning and reordering, function cloning and program instrumentation2nd International Workshop on GCC Research Opportunities (GROW'10), Jan 2010, Pisa, Italy
Communication dans un congrès
inria-00451106v1
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Synchronization of Periodic ClocksACM Conference on Embedded Software (EMSOFT), 2005, Jersey City, NJ, United States. 339--342 (short paper)
Communication dans un congrès
hal-01257295v1
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On the Effectiveness of Register Moves to Minimise Post-Pass Unrolling in Software Pipelined LoopsHPCS 2012 : International Conference on High Performance Computing & Simulation, Pr Waleed Smari, Jul 2012, Madrid, Spain
Communication dans un congrès
hal-00716183v1
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Application of Storage Mapping Optimization to Register PromotionIntl. Conf. on Supercomputing (ICS), Jun 2004, St-Malo, France. pp.247--256
Communication dans un congrès
hal-01257305v1
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Loop Unrolling Minimisation in the Presence of Multiple Register Types: a Viable Alternative to Modulo Variable ExpansionHPCS 2011 - International Conference on High Performance Computing Simulation, Jul 2011, Istanbul, Turkey. ⟨10.1109/HPCSim.2011.5999826⟩
Communication dans un congrès
hal-00699588v1
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AP+SOMT: Agent-Programming Combined with Self-Organized Multi-ThreadingWorkshop on Complexity-Effective Design at ISCA 31, Jun 2004, Munich/Germany
Communication dans un congrès
inria-00001107v1
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Collective OptimizationHiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_5⟩
Communication dans un congrès
inria-00445326v1
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A Conservative Approach to Handle Full Functions in the Polyhedral Model[Research Report] RR-6814, INRIA. 2008, pp.16
Rapport
inria-00356818v1
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Transitive Closures of Affine Integer Tuple Relations and their Overapproximations[Research Report] RR-7560, INRIA. 2011
Rapport
inria-00578052v1
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Computing the transitive closure of a union of affine integer tuple relationsConference on Combinatorial Optimization and Applications, Jun 2009, Huangshan, China. p98-109
Communication dans un congrès
hal-00575959v1
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Collective Tuning Initiative: automating and accelerating development and optimization of computing systemsGCC Developers' Summit, Jun 2009, Montreal, Canada
Communication dans un congrès
inria-00436029v2
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Enabling more optimizations in GRAPHITE: ignoring memory-based dependencesProceedings of the 8th GCC Developper's Summit, Oct 2010, Ottawa, Canada
Communication dans un congrès
inria-00551509v1
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Adsorption-induced fibronectin aggregation and fibrillogenesisJournal of Colloid and Interface Science, 2006, 298, pp.132-144
Article dans une revue
inria-00001063v1
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The Rebirth of Neural NetworksACM. International Symposium on Computer Architecture, Jun 2010, Saint Malo, France. 2010
Document associé à des manifestations scientifiques
inria-00535554v1
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DiST: A Simple, Reliable and Scalable Method to Significantly Reduce Processor Architecture Simulation TimeInternational Conference on Measurement and Modeling of Computer Systems, ACM SIGMETRICS, 2003, San Diego, California, United States
Communication dans un congrès
hal-01257307v1
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Decomposing Meeting Graph Circuits to Minimise Kernel Loop Unrolling9th Workshop on Optimizations for DSP and Embedded Systems (ODES-9), In conjunction with: International Symposium on Code Generation and Optimization (CGO), Apr 2011, Chamonix, France. pp.8
Communication dans un congrès
inria-00637938v1
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Parametric Multi-Level Tiling of Imperfectly Nested Loops23rd International Conference on Supercomputing, Jun 2009, Yorkton Heights, New York, United States
Communication dans un congrès
hal-00645328v1
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