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260 résultats
Interval matrix multiplication on parallel architecturesSCAN 2012: 15th GAMM-IMACS International Symposium on Scientific Computing, Computer Arithmetic and Verified Numerical Computations, Sep 2012, Novosibirsk, Russia
Communication dans un congrès
hal-00750022v1
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Practical polynomial factoring in polynomial time.Proceedings of ISSAC 2011, 2011, United States. pp.163-170
Communication dans un congrès
hal-00650391v1
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Faster Fully Homomorphic EncryptionProceedings of ASIACRYPT 2010, 2010, Singapore. pp.377--394
Communication dans un congrès
hal-00640633v1
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Worst Cases of a Periodic Function for Large Arguments18th IEEE Symposium in Computer Arithmetic, Jun 2007, Montpellier, France. pp.133-140, ⟨10.1109/ARITH.2007.37⟩
Communication dans un congrès
inria-00126474v2
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A proposal for the C++ standard : Bool_set, multi-valued logic[Research Report] RR-5967, INRIA. 2006, pp.22
Rapport
inria-00089230v2
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Improved Analysis of Kannan's Shortest Lattice Vector AlgorithmAdvances in Cryptology - Crypto'07, Aug 2007, Santa Barbara, United States. pp.170-186, ⟨10.1007/978-3-540-74143-5_10⟩
Communication dans un congrès
inria-00145049v2
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A Taylor Function Calculus for Hybrid System Analysis: Validation in CoqNSV-3: Third International Workshop on Numerical Software Verification., Fainekos, Georgios and Goubault, Eric and Putot, Sylvie, Jul 2010, Edinburgh, United Kingdom
Communication dans un congrès
inria-00473270v1
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Fonctions élémentaires : algorithmes et implémentations efficaces pour l'arrondi correct en double précisionModélisation et simulation. Ecole normale supérieure de lyon - ENS LYON, 2003. Français. ⟨NNT : ⟩
Thèse
tel-00006022v1
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From Rounding Error Estimation to Automatic Correction with Automatic DifferentiationRR-3967, INRIA. 2000
Rapport
inria-00072681v1
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Additive Symmetric: the Non-Negative CaseTheoretical Computer Science, 2003, 291 (2), pp.143-157. ⟨10.1016/S0304-3975(02)00223-2⟩
Article dans une revue
inria-00072516v1
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A 128-Tap Complex FIR Filter Processing 20 Giga-Samples/s in a Single FPGA44th Conference on signals, systems and computers, United States
Communication dans un congrès
ensl-00542950v1
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Computing specified generators of structured matrix inverses35th International Symposium on Symbolic and Algebraic Computation (ISSAC 2010), Jul 2010, Münich, Germany. ⟨10.1145/1837934.1837988⟩
Communication dans un congrès
ensl-00450272v1
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Rigorous and efficient short lattice vectors enumerationAsiacrypt 2008, 2008, Australia. pp.390-405
Communication dans un congrès
hal-00550983v1
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On the computation of correctly-rounded sumsIEEE Transactions on Computers, 2012, 61 (3), p. 289-298. ⟨10.1109/TC.2011.27⟩
Article dans une revue
ensl-00331519v2
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Fonctions élémentaires en virgule flottante pour les accélérateurs reconfigurablesRevue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, 2008, Architecture des Ordinateurs, 27 (6), pp.673-698. ⟨10.3166/tsi.27.673-698⟩
Article dans une revue
inria-00424001v1
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Accelerating Correctly Rounded Floating-PointDivision when the Divisor is Known in AdvanceIEEE Transactions on Computers, 2004, 53 (8), pp.1069- 1072. ⟨10.1109/TC.2004.37⟩
Article dans une revue
ensl-00087465v1
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Division by Constant for the ST100 DSP Microprocessor[Research Report] RR-5340, LIP RR-2004-45, INRIA, LIP. 2004, pp.14
Rapport
inria-00070661v1
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Multiplication Algorithms for Radix-$2$ RN-Codings and Two's Complement Numbers[Research Report] RR-5511, LIP RR-2005-05, INRIA, LIP. 2005, pp.13
Rapport
inria-00070495v1
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Discussions on an Interval Arithmetic Standard at Dagstuhl Seminar 08021Dagstuhl Seminar 08021: Numerical Validation in Current Hardware Architectures, Cuyt, Annie and Krämer, Walter and Luther, Wolfram and Markstein, Peter, Jan 2008, Dagstuhl, Germany. pp.1-6, ⟨10.1007/978-3-642-01591-5_1⟩
Communication dans un congrès
inria-00545059v1
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Efficient Public-Key Encryption Based on Ideal Lattices (Extended Abstract)Asiacrypt 2009, 2009, Japan. pp.617-635
Communication dans un congrès
hal-00550978v1
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Worst-Case Hermite-Korkine-Zolotarev Reduced Lattice Bases[Research Report] RR-6422, INRIA. 2008, pp.25
Rapport
inria-00211875v2
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Accelerated Shift-and-Add algorithmsReliable Computing, 2000, 6 (2), pp.193-205. ⟨10.1023/A:1009921407000⟩
Article dans une revue
inria-00545004v1
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Accelerating lattice reduction with FPGAsFirst International Conference on Cryptology and Information Security in Latin America (LATINCRYPT'10), Aug 2010, Puebla, Mexico. pp.124-143, ⟨10.1007/978-3-642-14712-8_8⟩
Communication dans un congrès
inria-00539929v1
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Bringing fast floating-point arithmetic into embedded integer processorsHiPEAC Info, 2010, 22, pp.11-12
Article dans une revue
ensl-00551245v1
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Optimizing correctly-rounded reciprocal square roots for embedded VLIW coresAsilomar Conference on Signals, Systems, and Computers, Nov 2009, United States
Communication dans un congrès
ensl-00391185v2
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Small Multiplier-based Multiplication and Division Operators for Virtex-II Devices[Research Report] RR-4494, INRIA. 2002
Rapport
inria-00072094v1
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Evaluation de polynômes et de fractions rationnelles sur FPGA avec des opérateurs à additions et décalages en grande base[Rapport de recherche] RR-5437, LIP RR-2004-62, INRIA, LIP. 2004, pp.15
Rapport
inria-00070570v1
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A correctly rounded implementationof the exponential function on the Intel Itanium architecture[Research Report] RR-5024, LIP RR 2003-54, INRIA, LIP. 2003
Rapport
inria-00071560v1
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Fast and correctly rounded logarithms in double-precision[Research Report] RR-5682, LIP RR-2005-37, INRIA, LIP. 2005, pp.15
Rapport
inria-00070331v1
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Digital ArithmeticBenjamin Wah. Wiley Encyclopedia of Computer Science and Engineering, Wiley, pp.935-948, 2009
Chapitre d'ouvrage
ensl-00542215v1
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