In this paper, we give a new formulation of acyclic scheduling problem under registers and resources constraints in multiple instructions issuing processors (VLIW and superscalar). Given a direct acyclic data dependence graph G = (V; E), the complexity of our integer linear programming model is bounded ) variables and O(jEj + jV j ) constraints according to a target architecture description. This complexity is better than the complexity of the existing techniques which includes a worst total schedule time factor.